全球速讯：linux中gmake是什么

#Comments are prefixed with the "#" symbol#A variable assignmentFOO = "hello there!"#A rule creating target "test", with "test.c" as a prerequisitetest: test.c # The contents of a rule is called the "recipe", and is # typically composed of one or more shell commands. # It must be indented from the target name (historically with # tabs, spaces are permitted) # Using the variable "FOO" echo $(FOO) # Calling the C compiler using a predefined variable naming # the default C compiler, "$(CC)" $(CC) test.c -o test

FOO = oneFOO += two# FOO is now "one two"FOO = oneFOO = $(FOO)two# FOO is now "onetwo"

FOO = 1BAR = $(FOO)FOO = 2# prints BAR=2$(info BAR=$(BAR))

FOO = 1BAR := $(FOO)FOO = 2# prints BAR=1$(info BAR=$(BAR))

$(info YOLO variable = $(YOLO))

$ YOLO="hello there!" makeYOLO variable = hello there!make: *** No targets.  Stop.

#默认CC为gccCC ? = gcc

$ CFLAGS="-Werror=conversion -Werror=double-promotion" make

# any value set elsewhereYOLO = "not overridden"$(info $(YOLO))

# setting "YOLO" to different values in the environment + makefile + overriding# variable, yields the overriding value$ YOLO="environment set" make YOLO="overridden!!"overridden!!make: *** No targets.  Stop.

# set the -g value to CFLAGS# applies to the prog.o/foo.o/bar.o recipes too!prog : CFLAGS = -gprog : prog.o foo.o bar.o echo $(CFLAGS) # will print "-g"

$(CC) - the C compiler (gcc)$(AR) - archive program (ar)$(CFLAGS) - flags for the C compilerFull list here:https://www.gnu.org/software/make/manual/html_node/Implicit-Variables.html

# $@ : the target name, here it would be "test.txt"test.txt: echo HEYO > $@# $^ : name of all the prerequisitesall.zip: foo.txt test.txt # run the gzip command with all the prerequisites "$^", outputting to the # name of the target, "$@" gzip -c $^ > $@See more at: https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html

arget: prerequisite recipe

# make the "test.txt" and "all.zip" targetsmake test.txt all.zip

# the "all" rule that builds and tests. Note that it"s listed first to make it# the default rule.PHONY: allall: build test# compile foo.c into a program "foo"foo: foo.c $(CC) foo.c -o foo# compile foo-lib.c into a library "foo.a"foo.a: foo-lib.c # compile the object file $(CC) foo-lib.c -c foo-lib.o # use ar to create a static library containing our object file. using the # "$@" variable here to specify the rule target "foo.a" $(AR) rcs $@ foo-lib.o# a phony rule that builds our project; just contains a prerequisite of the# library + program.PHONY: buildbuild: foo foo.a# a phony rule that runs our test harness. has the "build" target as a# prerequisite! Make will make sure (pardon the pun) the build rule executes# first.PHONY: testtest: build ./run-tests.sh

# this will compile "test.c" with the default $(CC), $(CFLAGS), into the program# "test". it will handle prerequisite tracking on test.ctest: test.oFull list of implicit rules here:https://www.gnu.org/software/make/manual/html_node/Catalogue-of-Rules.html

# Note the use of the "$<" automatic variable, specifying the first# prerequisite, which is the .c file%.o: %.c $(CC) -c $< -o $@

OBJ_FILES = foo.o bar.o# Use CC to link foo.o + bar.o into "program". Note the use of the "$^"# automatic variable, specifying ALL the prerequisites (all the OBJ_FILES)# should be part of the link commandprogram: $(OBJ_FILES)    $(CC) -o $@ $^

foo.o: foo.c # use automatic variables for the input and output file names $(CC) $^ -c $@

# these are the compiler flags for emitting the dependency tracking file. Note# the usage of the "$<" automatic variableDEPFLAGS = -MMD -MP -MF $<.dtest.o: test.c    $(CC) $(DEPFLAGS) $< -c $@# bring in the prerequisites by including all the .d files. prefix the line with# "-" to prevent an error if any of the files do not exist-include $(wildcard *.d)

OUTPUT_DIR = build# output the .o to the build directory, which we add as an order-only# prerequisite- anything right of the | pipe is considered order-only$(OUTPUT_DIR)/test.o: test.c | $(OUTPUT_DIR) $(CC) -c $^ -o $@# rule to make the directory$(OUTPUT_DIR): mkdir -p $@

foo.txt: # a simple recipe echo HEYO > $@

.PHONY: cleanclean: # we don"t care if rm fails -rm -r ./build

clean: @# this recipe will just print "About to clean everything!" @# prefixing the shell comment lines "#" here also prevents them from @# appearing during execution @echo About to clean everything!

USER = linusprint-user: # print out the shell variable $USER echo $$USER # print out the make variable USER echo $(USER)

FILES=$(wildcard *.c)# you can combine function calls; here we strip the suffix off of $(FILES) with# the $(basename) function, then add the .o suffixO_FILES=$(addsuffix .o,$(basename $(FILES)))# note that the GNU Make Manual suggests an alternate form for this particular# operation:O_FILES=$(FILES:.c=.o)

reverse = $(2) $(1)foo = $(call reverse,a,b)# recursive wildcard (use it instead of $(shell find . -name "*.c"))# taken from https://stackoverflow.com/a/18258352rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))C_FILES = $(call rwildcard,.,*.c)

FOO=yoloifeq ($(FOO),yolo)$(info foo is yolo!)else$(info foo is not yolo :( )endif# testing if a variable is set; unset variables are emptyifneq ($(FOO),)  # checking if FOO is blank$(info FOO is unset)endif# "complex conditional"ifeq ($(FOO),yolo)$(info foo is yolo)else ifeq ($(FOO), heyo)$(info foo is heyo)else$(info foo is not yolo or heyo :( )endif

# generate rules for xml->json in some weird worldFILES = $(wildcard inputfile/*.xml)# create a user-defined function that generates rulesdefine GENERATE_RULE =$(eval# prereq rule for creating output directory$(1)_OUT_DIR = $(dir $(1))/$(1)_out$(1)_OUT_DIR: mkdir -p $@# rule that calls a script on the input file and produces $@ target$(1)_OUT_DIR/$(1).json: $(1) | $(1)_OUT_DIR ./convert-xml-to-json.sh $(1) $@)# add the target to the all ruleall: $(1)_OUT_DIR/$(1).jsonendef# produce the rules.PHONY: allall:$(foreach file,$(FILES),$(call GENERATE_RULE,$(file)))

# This makefile should be invoked from the temporary build directory, eg:# $ mkdir -p build && cd ./build && make -f ../Makefile# Derive the directory containing this MakefileMAKEFILE_DIR = $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))# now inform Make we should look for prerequisites from the root directory as# well as the cwdVPATH += $(MAKEFILE_DIR)SRC_FILES = $(wildcard $(MAKEFILE_DIR)/src/*.c)# Set the obj file paths to be relative to the cwdOBJ_FILES = $(subst $(MAKEFILE_DIR)/,,$(SRC_FILES:.c=.o))# now we can continue as if Make was running from the root directory, and not a# subdirectory# $(OBJ_FILES) will be built by the pattern rule belowfoo.a: $(OBJ_FILES) $(AR) rcs $@ $(OBJ_FILES)# pattern rule; since we added ROOT_DIR to VPATH, Make can find prerequisites# like `src/test.c` when running from the build directory!%.o: %.c # create the directory tree for the output file   echo $@ mkdir -p $(dir $@) # compile $(CC) -c $^ -o $@

# our tools are stored in tools.tar.gz, and downloaded from a serverTOOLS_ARCHIVE = tools.tar.gzTOOLS_URL = https://httpbin.org/get# the rule to download the tools using wget$(TOOLS_ARCHIVE): wget $(TOOLS_URL) -O $(TOOLS_ARCHIVE)# rule to unpack themtools-unpacked.dummy: $(TOOLS_ARCHIVE) # running this command results in a directory.. but how do we know it # completed, without a file to track? tar xzvf $^ # use the touch command to record completion in a dummy file touch $@

ifeq ($(CC),clang)$(error whoops, clang not supported!)endif

# Makefile for building the "example" binary from C sources# Verbose flagifeq ($(V),1)Q :=elseQ := @endif# The build folder, for all generated output. This should normally be included# in a .gitignore ruleBUILD_FOLDER := build# Default all rule will build the "example" target, which here is an executable.PHONY:all: $(BUILD_FOLDER)/example# List of C source files. Putting this in a separate variable, with a file on# each line, makes it easy to add files later (and makes it easier to see# additions in pull requests). Larger projects might use a wildcard to locate# source files automatically.SRC_FILES = \    src/example.c \    src/main.c# Generate a list of .o files from the .c files. Prefix them with the build# folder to output the files thereOBJ_FILES = $(addprefix $(BUILD_FOLDER)/,$(SRC_FILES:.c=.o))# Generate a list of depfiles, used to track includes. The file name is the same# as the object files with the .d extension addedDEP_FILES = $(addsuffix .d,$(OBJ_FILES))# Flags to generate the .d dependency-tracking files when we compile.  It"s# named the same as the target file with the .d extensionDEPFLAGS = -MMD -MP -MF $@.d# Include the dependency tracking files-include $(DEP_FILES)# List of include dirs. These are put into CFLAGS.INCLUDE_DIRS = \    src/# Prefix the include dirs with "-I" when passing them to the compilerCFLAGS += $(addprefix -I,$(INCLUDE_DIRS))# Set some compiler flags we need. Note that we"re appending to the CFLAGS# variableCFLAGS += \    -std=c11 \    -Wall \    -Werror \    -ffunction-sections -fdata-sections \    -Og \    -g3# Our project requires some linker flags: garbage collect sections, output a# .map fileLDFLAGS += \    -Wl,--gc-sections,-Map,$@.map# Set LDLIBS to specify linking with libm, the math libraryLDLIBS += \    -lm# The rule for compiling the SRC_FILES into OBJ_FILES$(BUILD_FOLDER)/%.o: %.c @echo Compiling $(notdir $<) @# Create the folder structure for the output file @mkdir -p $(dir $@) $(Q) $(CC) $(CFLAGS) $(DEPFLAGS) -c $< -o $@# The rule for building the executable "example", using OBJ_FILES as# prerequisites. Since we"re not relying on an implicit rule, we need to# explicity list CFLAGS, LDFLAGS, LDLIBS$(BUILD_FOLDER)/example: $(OBJ_FILES) @echo Linking $(notdir $@) $(Q) $(CC) $(CFLAGS) $(LDFLAGS) $^ $(LDLIBS) -o $@# Remove debug information for a smaller executable. An embedded project might# instead using [arm-none-eabi-]objcopy to convert the ELF file to a raw binary# suitable to be written to an embedded deviceSTRIPPED_OUTPUT = $(BUILD_FOLDER)/example-stripped$(STRIPPED_OUTPUT): $(BUILD_FOLDER)/example @echo Stripping $(notdir $@) $(Q)objcopy --strip-debug $^ $@# Since all our generated output is placed into the build folder, our clean rule# is simple. Prefix the recipe line with "-" to not error if the build folder# doesn"t exist (the -f flag for rm also has this effect).PHONY: cleanclean: - rm -rf $(BUILD_FOLDER)